ICs, packaging technology is a very critical loop

1、 Technical introduction

Encapsulation can also be said of installing the housing used for the semiconductor integrated circuit chip, which not only functions to secure, fix, seal, protect the chip and enhance thermal conductivity, but also as a bridge to communicate the chip's inner world with the external circuit - the contacts on the chip are connected with wires to the pins of the packaging housing, These pins, in turn, make connections to other devices through the wires on the printed circuit board. Therefore, packaging technology is a very critical loop for many ICs products.

Most of the CPU packages adopted are packaged in insulating plastic or ceramic materials, which can play the role of sealing and improving the electrothermal performance of the chip. Since now the processor chip has more and more internal frequency, more and more functions, more and more pins, and the shape of the package is changing constantly.

2、 Caveats

1. The ratio of chip area to encapsulation area is to improve encapsulation efficiency as close as 1:1

2. Pins should be as short as possible to reduce delay and pin to pin distance as far as possible to guarantee mutual non-interference and improve performance

3. Based on the requirement of heat dissipation, the thinner the package the better

As an important component of computers, the performance of CPU directly affects the overall performance of computers. And the last and critical step in the manufacturing process of CPUs is the packaging technology of CPUs, which uses different packaging technologies and has large gaps in performance. Only high-quality packaging technology produces a perfect CPU product.

3、 Primary encapsulation techniques

Dip Technique
Dip Technique

The dip package (dual in line Package), also called double column direct interpolation packaging technology, refers to an integrated circuit chip encapsulated in double column direct format, the vast majority of small - and medium-scale integrated circuits use this package form, and its pin number generally does not exceed 100. The CPU chip with the dip package has two rows of pins and needs to be inserted into a chip socket with a dip structure. Of course, welding can also be performed directly on a board with the same weld hole number and geometric arrangement. The dip encapsulated chip should be particularly careful when pluggable from the chip socket so as not to damage the footings. Dip encapsulating constructs come in the form of: multi-layered ceramic dual column direct insertion dip, single-layer ceramic dual column direct insertion dip, lead frame dip, etc.

The dip encapsulation has the following characteristics:

1. Fit perforated welding on PCB (printed circuit board) for easy operation.

2. The ratio between chip area and encapsulation area is larger, so the volume.

QFP / PFP Technique
QFP / PFP Technique

Chinese meaning of QFP technology called Fang type flat [1] flat packaging technology (Plastic Quad flag packaging), the chip pin of QFP packaging. The distance between them is small, the feet are thin, the general large scale or ultra large scale integrated circuit all adopt this package form, the number of pins is generally above 100. The SMD technique must also be employed to weld the chip to the motherboard. The SMD technique must also be employed to weld the chip to the motherboard.

The QFP / PFP encapsulation has the following characteristics:

1. Adaptation of the SMD surface mounting technique install wiring on the PCB board.

2. Encapsulating external form with smaller dimensions and reduced parasitism parameters for high frequency applications.

3. Operation convenience and high reliability.

4. The ratio between chip area and encapsulation area is smaller. This package is adopted by the 80286, 80386, and some 486 motherboards in the Intel Series CPU.

PGA Technique
PGA Technique

The technique is also called the needle grid array encapsulation technique (ceramic pin grid Arrau package), the chip enclosed by this technology has multiple square paroxysmal needle inserts inside and outside, each square paroxysmal needle is arranged at a certain distance along the four weeks of the chip, and can be arranged in 2 to 5 turns depending on the number of tubes and feet. When installed, the chip is inserted into a specialized PGA socket. To enable a more convenient installation and disassembly of the CPU, starting with the 486 chip, the out A ZIF CPU socket was developed to specifically meet the requirements of the PGA package CPU on installation and disassembly. This technique is generally used below more frequent occasions for pluggable operations.

PGA encapsulation has the following characteristics:

1. Pluggable operation is more convenient and reliable;

2. Amenable to higher frequencies;

3. If a ceramic substrate with good thermal conductivity is used, it can also be adapted to high-speed and high-power device requirements;

4. Since this package has an outwardly projecting pin, it is generally acceptable to adopt an insert type mounting but not a surface mounting;

5. As with ceramic substrates, the price is again relatively high and therefore mostly for more special purposes. It is further divided into two types, display pin type and surface mount type.

BGA Technique
BGA Technique

BGA technique (ball grid array package) that is, ball gate array packaging technology.  The emergence of this technology has become the best choice for high-density, high-performance, multi pin packaging such as CPU, motherboard south, and North Bridge chips. 

 The area occupied by BGA packaging is relatively large Adopted a controlled collapse chip welding method so that its electrothermal performance could be improved. Addi - tionally the assembly of this technique can be weld coplanarly, allowing for a substantial increase in encapsulation reliability; And the encapsulated CPU implemented by this technology has a small signal transfer delay, and the adaptation frequency can be improved greatly.

BGA encapsulation has the following characteristics:

1. The number of I / O pins although increased, the distance between pins is much larger than the QFP packaging way, which improves the finished product rate

2. Although the power consumption of BGA is increased, it is possible to improve the electrothermal performance since a controllable collapse chip based welding is adopted

3. Small delay in signal transmission and greatly increased frequency of adaptation

4. Assembly can be welded coplanarly with greatly improved reliability

Inadequacies of BGA encapsulation: BGA encapsulation is still the same as QFP, PGA, occupied the substrate area is too large; The warping problem of plastic BGA packaging is its main drawback, i.e., the coplanarity problem of tin spheres. The criteria for coplanarity are to reduce warping and improve the characteristics of BGA encapsulation, and plastic, viscosupply, and substrate materials should be studied and optimized. At the same time, because of the high cost of the substrate, which makes it expensive.

SFF Technique
SFF Technique

SFF is short for small form factor, Intel called small packaging technology. Intel's small packaging technology is a special technology adopted in the process of encapsulating mobile processors, and can reduce the package size to about 40% of its ordinary size without compromising processor performance, thus bringing the other components within the mobile product to shrink together in size, and ultimately allowing the terminal product to be lighter, smaller, and fadlike, And support the design of a richer appearance and material.